I. Field of the Invention
This invention relates to a limiter circuit and, more particularly, to a limiter circuit responding to input digital data and performing a limiting operation thereon to produce output digital data.
II. Description of the Prior Art
Such a limiter circuit is disclosed in Japanese Patent Application Laid Open No. Sho 60-220402 and shown FIG. 1.
In FIG. 1, reference numeral 101 depicts an arithmetic operation unit, 201 upper limit data, and 202 lower limit data. This limiter circuit further includes a first comparator 102 comparing the upper limit value 201 with the data derived from the arithmetic operation unit 101, a second comparator 103 comparing the lower limit value 202 with the data from the arithmetic operation unit 101, and a selector 104 selects and thus outputs either one of the output of the arithmetic operation unit 101, the upper limit value 201 and the lower limit value 202, in response to the comparison outputs of the comparators 102 and 103.
In operation, when the output of the arithmetic operation unit 101 is within a range determined by the upper limit value 201 and the lower limit value 202, the outputs of the comparator 102 and 103 take a first state. The selector 104 thereby selects and produces the output of the arithmetic operation unit 101. When the output of the arithmetic operation circuit 101 is beyond the above range, the outputs of the comparators 102 and 103 take a second state to cause the selector 104 to selects the upper limit value 201. Finally, the arithmetic output does not reach the above range, the selector 104 selects the lower limit value 202 in response to a third state indicated by the outputs of the comparators 102 and 103.
In comparison operation of the comparators 102 and 103, the comparator 102 outputs the high level when the output of the arithmetic operation circuit 101 is larger than the upper limit value 201 and the low level when the former is equal to or smaller than the latter. On the other hand, the comparator 103 produces the high level output when the output of the arithmetic operation circuit 101 is smaller than the lower limit value 202 and the low level output when the former is equal to or larger than the latter.
Accordingly, the second state is represented by the high level of the comparator 102 and the low level of the comparator 103. The third state is represented by the low level of the comparator 102 and the high level of the comparator 103. The first state is represented by the low levels of the comparators 102 and 103.
The limiter circuit thus constructed can be applied to a digital signal processing apparatus, an image processing apparatus and the like. Such an apparatus requires a high-speed processing operation, as well known in the art. The limiter circuit employed such an apparatus is thus also required to perform a high-speed limiting operation. However, the limiter circuit of FIG. 1 operates at a relatively low speed.
More specifically, each of the comparators 102 and 103 performs the comparison operation on digital data and is thus required to compare every bit thereof in sequence from the least significant bit to the most significant bit. For this reason, each comparator takes a relatively long comparison time. Moreover, it depends on the bit range of the data.
For example, a comparator having a 16-bit input produces a delay time approximately four times as large as a comparator having a 4-bit input, and a comparator having 32-bit input produces a delay time approximately 6 times as large as a comparator having 5-bit input. Therefore, it is difficult to realize high-speed signal processing by the limiter circuit as shown in FIG. 1.